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Lucas Szajek is a Senior FPGA Engineer at MemComputing with more than 20 years of experience designing, validating, and delivering high-performance FPGA systems that have to work the first time and keep working in the field. He most recently served as an FPGA Technical Lead at ASML in San Diego, where he led development for critical droplet and plasma generation subsystems used in EUV lithography, taking designs from early architecture and requirements through RTL, verification, integration, and production bring-up.
Before ASML, Lucas built and shipped advanced video and networking platforms across Cisco and Synamedia, including complex FPGA subsystems with PCIe, 10G Ethernet, high-speed memory interfaces, SDI video up to 12G, Video-over-IP standards, transport stream processing, and video encryption and decryption. He has also led FPGA teams and product development at Muxlab and iS5 Communications, and earlier in his career contributed to encoder and high-reliability programs at Scientific Atlanta and MDA, including work on reliability and SEU recovery techniques for space-grade systems.
Lucas holds an M.Phil. focused on reconfigurable parallel computing and has published research on FPGA reliability. At MemComputing, he brings deep hands-on RTL expertise and calm technical leadership to turn ambitious performance targets into robust, shippable FPGA architectures.