Manav Raina is a hardware and RTL design engineer at MemComputing with more than 15 years of experience turning ambitious specs into silicon- and FPGA-proven designs. He works across the full cycle from architecture and RTL development to verification, integration, and lab bring-up and is known for being the person you want on the team when a design has to be elegant on paper and solid in the lab.

Before joining MemComputing, Manav was a Staff RTL Engineer at Qualcomm Technologies, where he helped deliver ultra-low-power features for IoT and BLE and contributed to advanced WiFi and cellular programs. His background includes low-power design techniques such as clock gating and multi-voltage domains, rigorous CDC/RDC practices, and high-throughput FPGA development on Xilinx platforms. He has also built large data-path systems, including a 100GE packet sniffer, and led a proof-of-concept effort for a low-cost, high scan-rate 2D LiDAR approach.

Manav holds an MS in Electrical Engineering with a focus on VLSI design. At MemComputing, he brings deep RTL craftsmanship and a practical, hands-on mindset—bridging design, tools, and hardware to help deliver robust, production-ready systems.